Analog and Mixed-Signal Circuit Design
External reference: https://openalex.org/T10323
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Two-step SAR ADC reduces capacitance and power 12-bit, 10 MS/s two-step sub-ranging SAR ADC with top-plate dividing architecture for residue amplification, achieving 65.7 dB SNDR and 14.5 fJ/conversion-step FoM in 65 nm CMOS.
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Cost-effective FPGA platform records electrophysiological signals faithfully FPGA-based modular platform for cost-effective electrophysiological signal acquisition with soft core processor, real-time conditioning, and performance validation against commercial systems.